Speech and Audio Coding for Wireless and Network Applications

The Springer International Series in Engineering and Computer Science

Book 224
Springer Science & Business Media
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Speech and Audio Coding for Wireless and Network Applications contains 34 chapters, loosely grouped into six topical areas. The chapters in this volume reflect the progress and present the state of the art in low-bit-rate speech coding, primarily at bit rates from 2.4 kbit/s to 16 kbit/s. Together they represent important contributions from leading researchers in the speech coding community.
Speech and Audio Coding for Wireless and Network Applications contains contributions describing technologies that are under consideration as standards for such applications as digital cellular communications (the half-rate American and European coding standards). A brief Introduction is followed by a section dedicated to low-delay speech coding, a research direction which emerged as a result of the CCITT requirement for a universal low-delay 16 kbit/s speech coding technology and now continues with the objective of achieving toll quality with moderate delay at a rate of 8 kbit/s. A section on the important topic of speech quality evaluation is then presented. This is followed by a section on speech coding for wireless transmission, and a section on audio coding which covers not only 7 kHz bandwidth speech, but also wideband coding applicable to high fidelity music. The book concludes with a section on speech coding for noisy transmission channels, followed by a section addressing future research directions.
Speech and Audio Coding for Wireless and Network Applications presents a cross-section of the key contributions in speech and audio coding which have emerged recently. For this reason, the book is a valuable reference for all researchers and graduate students in the speech coding community.
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Additional Information

Publisher
Springer Science & Business Media
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Published on
Dec 6, 2012
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Pages
283
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ISBN
9781461532323
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Best For
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Language
English
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Genres
Technology & Engineering / Electrical
Technology & Engineering / Electronics / General
Technology & Engineering / Imaging Systems
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Content Protection
This content is DRM protected.
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As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
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