Quadrature Frequency Generation for Wideband Wireless Applications

Springer
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This book describes design techniques for wideband quadrature LO generation for software defined radio transceivers, with frequencies spanning 4GHz to around 80GHz. The authors discuss several techniques that can be used to reduce the cost and/or power consumption of one of the key component of the RF front-end, the quadrature local oscillator. The discussion includes simple and useful insights into quadrature VCOs, along with numerous examples of practical techniques.
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Additional Information

Publisher
Springer
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Published on
Mar 10, 2015
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Pages
78
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ISBN
9783319137889
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Language
English
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Genres
Technology & Engineering / Electrical
Technology & Engineering / Electronics / Circuits / General
Technology & Engineering / Electronics / General
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Content Protection
This content is DRM protected.
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Smart and Flexible Digital-to-Analog Converters proposes new concepts and implementations for flexibility and self-correction of current-steering digital-to-analog converters (DACs) which allow the attainment of a wide range of functional and performance specifications, with a much reduced dependence on the fabrication process.

DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method.

This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance.

Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.“/p>

DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method.

This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance.

Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.

This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance.

Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.

Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.

"This is teaching at its best!"

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Want to learn the fundamentals of electronics in a fun, hands-on way? With Make: Electronics, you'll start working on real projects as soon as you crack open the book. Explore all of the key components and essential principles through a series of fascinating experiments. You'll build the circuits first, then learn the theory behind them!

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Discover by breaking things: experiment with components and learn from failure Set up a tricked-out project space: make a work area at home, equipped with the tools and parts you'll need Learn about key electronic components and their functions within a circuit Create an intrusion alarm, holiday lights, wearable electronic jewelry, audio processors, a reflex tester, and a combination lock Build an autonomous robot cart that can sense its environment and avoid obstacles Get clear, easy-to-understand explanations of what you're doing and why
Voltage-controlled oscillators (VCOs) with low phase noise are the most critical building block in high performance phase-locked loops (PLL). Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present. Design of High-Performance CMOS Voltage-Controlled Oscillators noise, analyzes the impact of the supply and substrate noise on the oscillator phase noise, and suggests techniques for reducing the jitter due to the supply and substrate noise.
The primary audience for Design of High-Performance CMOS Voltage-Controlled Oscillators is research workers and design engineers who concentrate on high performance communication circuits. This work will also be of interest to analog circuit designers.
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