Hot-Carrier Reliability of MOS VLSI Circuits

The Springer International Series in Engineering and Computer Science

Book 227
Springer Science & Business Media
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As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
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Additional Information

Publisher
Springer Science & Business Media
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Published on
Dec 6, 2012
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Pages
212
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ISBN
9781461532507
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Language
English
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Genres
Technology & Engineering / Electrical
Technology & Engineering / Electronics / Circuits / General
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Content Protection
This content is DRM protected.
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This book contains selected papers from the ONR Workshop on Parallel Algorithm Design and Program Transformation that took place at New York University, Courant Institute, from Aug. 30 to Sept. 1, 1991. The aim of the workshop was to bring together computer scientists in transformational programming and parallel algorithm design in order to encourage a sharing of ideas that might benefit both communities. It was hoped that exposurt: to algorithm design methods developed within the algorithm community would stimulate progress in software development for parallel architectures within the transformational community. It was also hoped that exposure to syntax directed methods and pragmatic programming concerns developed within the transformational community would encourage more realistic theoretical models of parallel architectures and more systematic and algebraic approaches to parallel algorithm design within the algorithm community. The workshop Organizers were Robert Paige, John Reif, and Ralph Wachter. The workshop was sponsored by the Office of Naval Research under grant number N00014-90-J-1421. There were 44 attendees, 28 presentations, and 5 system demonstrations. All attendees were invited to submit a paper for publication in the book. Each submitted paper was refereed by participants from the Workshop. The final decision on publication was made by the editors. There were several motivations for holding the workshop and for publishing papers contributed by its participants. Transformational programming and parallel computation are two emerging fields that may ultimately depend on each other for success.
Practical Low Power Digital VLSI Design emphasizes the optimization and trade-off techniques that involve power dissipation, in the hope that the readers are better prepared the next time they are presented with a low power design problem. The book highlights the basic principles, methodologies and techniques that are common to most CMOS digital designs. The advantages and disadvantages of a particular low power technique are discussed. Besides the classical area-performance trade-off, the impact to design cycle time, complexity, risk, testability and reusability are discussed. The wide impacts to all aspects of design are what make low power problems challenging and interesting. Heavy emphasis is given to top-down structured design style, with occasional coverage in the semicustom design methodology. The examples and design techniques cited have been known to be applied to production scale designs or laboratory settings. The goal of Practical Low Power Digital VLSI Design is to permit the readers to practice the low power techniques using current generation design style and process technology.
Practical Low Power Digital VLSI Design considers a wide range of design abstraction levels spanning circuit, logic, architecture and system. Substantial basic knowledge is provided for qualitative and quantitative analysis at the different design abstraction levels. Low power techniques are presented at the circuit, logic, architecture and system levels. Special techniques that are specific to some key areas of digital chip design are discussed as well as some of the low power techniques that are just appearing on the horizon.
Practical Low Power Digital VLSI Design will be of benefit to VLSI design engineers and students who have a fundamental knowledge of CMOS digital design.
This book has its roots in an idea first formulated by Barrie Gilbert in 1975. He showed how bipolar analog circuits can realize nonlinear and computational functions. This extended the analog art from linear to nonlinear applications, hence the name trans linear circuits. Not only did this new principle enable marvellous signal processing functions to be accurately implemented, but also the circuits were simple and practical. The perennial problems of analog Ie design, namely temperature sensitivity, processing spread, device nonlinearity and paracitic capacitance were solved to a large extent. Using the trans linear principle in circuit design requires changing your point of view in two ways. First, the grossly nonlinear characteristic of transistors is viewed as an asset rather than as a harmful property. Second, no longer are the signals represented by voltages, but by currents. In fact, the attendant voltage changes are distorted but, as they are very small, they are only of secondary interest. Understanding and analyzing a given trans linear circuit is fairly straightforward. But what about the converse situation: suppose you're given some nonlinear or computational function to implement? How to find a suitable translinear circuit realization? The general problem of analog circuit synthesis is a difficult one and is receiving much attention nowadays. Some years ago, I had the opportunity to investigate methods for designing bipolar trans linear circuits. It turned out that translinear networks have some unique topological properties. Using these properties it was possible to establish heuristic synthesis procedures.
Research in analog integrated circuits has recently gone in the direction of low-voltage (LV), low-power (LP) design, especially in the environment of portable systems where a low supply voltage, given by a single-cell battery, is used. These LV circuits have to show a reduced power consumption to maintain a longer battery lifetime as well. In this area, traditional voltage-mode techniques are going to be substituted by the current-mode approach, which has the recognized advantage to overcome the gain-bandwidth product limitation, typical of operational amplifiers. Then they do not require high voltage gains and have good performance in terms of speed, bandwidth and accuracy. Inside the current-mode architectures, the current-conveyor (CCII) can be considered the basic circuit block because all the active devices can be made of a suitable connection of one or two CCIIs. CCII is particularly attractive in portable systems, where LV LP constraints have to be taken into account. In fact, it suffers less from the limitation of low current utilisation, while showing full dynamic characteristics at reduced supplies (especially CMOS version) and good high frequency performance. Recent advances in integrated circuit technology have also highlighted the usefulness of CCII solutions in a large number of signal processing applications.
In Low Voltage, Low Power CMOS Current Conveyors, the authors start by giving a brief history of the first and second generation CC. Then, the second generation current-conveyor (CCII) will be considered as a building block in the main active feedback devices and in the implementation of simple analog functions, as an alternative to OA. In the next chapters, the design of CCII topologies will be considered, together with a further look into CCII modern solutions and future trends. The authors will, therefore, describe LV LP CCII implementations, their evolution towards differential and generalized topologies, and new possible CCII applications in some basic analog functions such as filters, impedance simulators and converters, oscillators, among others.
Being a concise and modern book on current conveyors, Low Voltage, Low Power CMOS Current Conveyors considers these kinds of devices both in a general environment and for low-voltage low-power applications. This book can constitute an excellent reference for analog designers and researchers and is suitable for use as a textbook in an advanced course on Microelectronics.
The intention of this book is to address a number of timely, performance-critical issues within the field of short-distance optical communications, from a circuit designer’s perspective. It discusses the major trade-offs the designer has to deal with in the development of monolithically integrated receivers in CMOS technologies. As such, it is based on Dr. Muller’s doctoral dissertation entitled “A Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications”, subm- ted to the School of Engineering of the École Polytechnique Fédérale de Lausanne (EPFL) in May 2006. The dissertation material has been enhanced by the presentation of a number of alternative design approaches and circuit topologies, providing exhaustive coverage of the state of the art in optical sho- distance receiver circuit design. The need for a new processor input/output (I/O) interface paradigm is dictated by ongoing te- nology scaling and the advent of multi-core systems. Indeed, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput, whereas the available bandwidth of the I/O interfaces is subject to much slower growth. Moving beyond - coming serial links to an optical data link paradigm for very short-distance (board-to-board and chip-- chip communications allows for considerable I/O interface bandwidth enhancement. Fully integrated silicon CMOS receivers are considered to be the technology of choice to lead this solution to economic success, because monolithic integration results in lower volume-manufacturing cost, improved yield and reduced assembly and test expenses.
"This is teaching at its best!"

--Hans Camenzind, inventor of the 555 timer (the world's most successful integrated circuit), and author of Much Ado About Almost Nothing: Man's Encounter with the Electron (Booklocker.com)

"A fabulous book: well written, well paced, fun, and informative. I also love the sense of humor. It's very good at disarming the fear. And it's gorgeous. I'll be recommending this book highly."

--Tom Igoe, author of Physical Computing and Making Things Talk

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