Computation Engineering: Applied Automata Theory and Logic

Springer Science & Business Media
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It takes more e?ort to verify that digital system designs are correct than it does to design them, and as systems get more complex the proportion of cost spent on veri?cation is increasing (one estimate is that veri?cation complexity rises as the square of design complexity). Although this veri?cation crisis was predicted decades ago, it is only recently that powerful methods based on mathematical logic and automata theory have come to the designers’ rescue. The ?rst such method was equivalence checking, which automates Boolean algebra calculations.Nextcamemodelchecking,whichcanautomatically verify that designs have – or don’t have – behaviours of interest speci?ed in temporal logic. Both these methods are available today in tools sold by all the major design automation vendors. It is an amazing fact that ideas like Boolean algebra and modal logic, originating frommathematicians andphilosophersbeforemodern computers were invented, have come to underlie computer aided tools for creating hardware designs. The recent success of ’formal’ approaches to hardware veri?cation has lead to the creation of a new methodology: assertion based design, in which formal properties are incorporated into designs and are then validated by a combination of dynamic simulation and static model checking. Two industrial strength property languages based on tem- ral logic are undergoing IEEE standardisation. It is not only hardwaredesignand veri?cation that is changing: new mathematical approaches to software veri?cation are starting to be - ployed. Microsoft provides windows driver developers with veri?cation tools based on symbolic methods.
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Additional Information

Publisher
Springer Science & Business Media
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Published on
Sep 10, 2006
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Pages
472
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ISBN
9780387325200
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Best For
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Language
English
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Genres
Computers / Computer Science
Computers / Information Technology
Mathematics / Discrete Mathematics
Mathematics / Logic
Technology & Engineering / Electrical
Technology & Engineering / Electronics / Circuits / General
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Content Protection
This content is DRM protected.
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The size of technically producible integrated circuits increases continuously. But the ability to design and verify these circuits does not keep up with this development. Therefore, today’s design ?ow has to be improved to achieve a higher productivity. In this book the current design methodology and ver- cation methodology are analyzed, a number of de?ciencies are identi?ed, and solutions are suggested. Improvements in the methodology as well as in the underlying algorithms are proposed. An in-depth presentation of preliminary concepts makes the book self-contained. Based on this foundation major - sign problems are targeted. In particular, a complete tool ?ow for Synthesis for Testability of SystemC descriptions is presented. The resulting circuits are completely testable and test pattern generation in polynomial time is possible. Veri?cation issues are covered in even more detail. A whole new paradigm for formal design veri?cation is suggested. This is based upon design und- standing, the automatic generation of properties, and powerful tool support for debugging failures. All these new techniques are empirically evaluated and - perimental results are provided. As a result, an enhanced design ?ow is created that provides more automation (i.e. better usability) and reduces the probability of introducing conceptual errors (i.e. higher robustness). Acknowledgments We would like to thank all members of the research group for computer arc- tecture in Bremen for the helpful discussions and the great atmosphere during work and research.
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