關於這本電子書
The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.
為這本電子書評分
請分享你的寶貴意見。
閱讀資訊
智能手機和平板電腦
手提電腦和電腦
你可以使用電腦的網絡瀏覽器聆聽在 Google Play 上購買的有聲書。
電子書閱讀器及其他裝置
如要在 Kobo 等電子墨水裝置上閱覽書籍，你需要下載檔案並傳輸到你的裝置。請按照說明中心的詳細指示，將檔案傳輸到支援的電子書閱讀器。
