Informazioni su questo ebook
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
Valutazioni e recensioni
4,0
2 recensioni
Valuta questo ebook
Dicci cosa ne pensi.
Informazioni sulla lettura
Smartphone e tablet
Installa l'app Google Play Libri per Android e iPad/iPhone. L'app verrà sincronizzata automaticamente con il tuo account e potrai leggere libri online oppure offline ovunque tu sia.
Laptop e computer
Puoi ascoltare gli audiolibri acquistati su Google Play usando il browser web del tuo computer.
eReader e altri dispositivi
Per leggere su dispositivi e-ink come Kobo e eReader, dovrai scaricare un file e trasferirlo sul dispositivo. Segui le istruzioni dettagliate del Centro assistenza per trasferire i file sugli eReader supportati.
